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Device Overview MC9S12G-Family
1.3.1
S12 16-Bit Central Processor Unit (CPU)
S12 CPU is a high-speed 16-bit processing unit:
? Full 16-bit data paths supports ef?cient arithmetic operation and high-speed math execution
? Includes many single-byte instructions. This allows much more ef?cient use of ROM space.
? Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
1.3.2
On-Chip Flash with ECC
On-chip ?ash memory on the MC9S12G-Family family features the following:
? Up to 240 Kbyte of program ?ash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
? Up to 4 Kbyte EEPROM
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 4 bytes
— Automated program and erase algorithm
— User margin level setting for reads
1.3.3
?
1.3.4
?
?
?
?
On-Chip SRAM
Up to 11 Kbytes of general-purpose RAM
Port Integration Module (PIM)
Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used
as general-purpose I/O
Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J
and AD on per-pin basis
Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis
and on BKGD pin
Control registers to enable/disable open-drain (wired-or) mode on ports S and M
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
43
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